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FEATURES Single +5 V Supply On-Chip /4 DQPSK Modulator Modulator Bypass Analog Mode Root-Raised Cosine Tx Filters, = 0.35 Two 10-Bit D/A Converters 4th Order Reconstruction Filters Differential Analog Outputs On-Chip Ramp Up/Down Power Control On-Chip Tx Offset Calibration Dual Mode Operation, Analog and Digital Very Low Power Dissipation, 30 mW typical Power Down Mode < 10 A On-Chip Voltage Reference 24-Pin SSOP APPLICATIONS American Digital Cellular Telephony American Analog Cellular Telephony
CMOS, ADC /4 DQPSK Baseband Transmit Port AD7011
GENERAL DESCRIPTION
The AD7011 is a complete low power, CMOS, /4 DQPSK modulator with single +5 V power supply. The part is designed to perform the baseband conversion of I and Q transmit waveforms in accordance with the American Digital Cellular Telephone system (TIA IS-54). The on-chip /4 Differential Quadrature Phase Shift Keying (DQPSK) digital modulator, which includes the root raised cosine filters, generates I and Q data in response to the transmit data stream. The AD7011 also contains ramp control envelope logic to shape the I and Q output waveforms when ramping up or down at the beginning or end of a transmit burst. Besides providing all the necessary logic to perform /4 DQPSK modulation, the part also provides reconstruction filters to smooth the DAC outputs, providing continuous time analog outputs. The AD7011 generates differential analog outputs for both the I and Q signals. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has transmit and receive power-down options. The AD7011 is housed in a space efficient 24-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DGND MCLK I BIN (Q DATA) ANALOG MODE SERIAL Q INTERFACE MODULATOR BYPASS I Tx DATA (I DATA) Tx CLK (FRAME) /4 DQPSK DIGITAL MODULATOR 10-BIT Q-DAC 10-BIT I-DAC RECONSTRUCTION FILTERS ITx ITx VDD VAA AGND
CALIBRATION CIRCUITRY
Q
RECONSTRUCTION FILTERS
QTx QTx
READY
AD7011
POWER
2.46V REFERENCE
BOUT
BYPASS
MODE1
MODE2
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
10%; Test = AGND = DGND = 0 V; Digital Mode, AA = VDD = +5 V fMCLK = 3.1104 MHz; Analog Mode, fMCLK = 2.56 MHz, POWER = VDD. All specifications are TMIN to TMAX unless otherwise noted.)
Parameter DIGITAL MODE TRANSMIT SPECIFICATIONS Number of Channels Output Signal Range Differential Output Range Signal Vector Magnitude2 Error Vector Magnitude2 Offset Vector Magnitude2 IS-54 Spurious Power2, 3 @ 30 kHz @ 60 kHz @ 90 kHz, 120 kHz ANALOG MODE SPECIFICATIONS No. of Channels Resolution Output Signal Range Differential Output Range DAC Update Rate SNR Differential Offset Error Group Delay Matching Between I & Q Outputs Coding Maximum and Minimum DAC Codes4 REFERENCE & CHANNEL SPECIFICATIONS Reference, VREF Reference Accuracy I and Q Gain Matching Power-Down Option LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH Output High Voltage VOL Output Low Voltage POWER SUPPLIES VDD IDD Transmit Section Active Transmit Section Powered Down5 AD7011ARS 2 VREF + VREF/4 +VREF/2 0.875 7.5% 1 2.5 0.5 2.5 -35 -30 -70 -65 -75 -70 2 10 VREF VREF/3 2VREF/3 160 60 55 15 30 Twos Complement +450/-450 2.46 5 0.2 Yes VDD - 0.9 0.9 10 10 VDD - 0.4 0.4 4.5/5.5 8 6 35 5 Units Test Conditions/Comments (ITx - ITx) and (QTx - QTx) For Each Analog Output I Channel = (ITx - ITx) and Q Channel = (QTx - QTx) Measured Differentially
AD7011-SPECIFICATIONS1 (V
Volts Volts Volts max % rms typ % rms max % typ % max dB typ dB max dB typ dB max dB typ dB max
(ITx - ITx) and (QTx - QTx) Bits Volts Volts kHz dB typ dB min mV max ns typ max/min Volts % dB max For Each Analog Output I Channel = (ITx - ITx) and Q Channel = (QTx - QTx) MCLK/16; fMCLK = 2.56 MHz Generating a 10 kHz Sine Wave Post Calibration
Measured @ 10 kHz Power = 0 V
V min V max FA max pF max V min V max V min/V max mA max mA typ A max A max POWER = VDD MCLK Active MCLK Inactive |IOUT| 40 A |IOUT| 1.6 mA
NOTES 1 Operating temperature ranges as follows: A Version: -40C to +85C. 2 See terminology. 3 Measured in continuous transmission and Burst Mode with the I and Q channels ramping up and down at the beginning and end of a burst. 4 Headroom must be allowed for the transmit DACs such that offsets in I & Q transmit channels can be calibrated out. Therefore, the full range of the I and Q DACs are not available to the user. The user should ensure that binary codes greater than or less than the maximum or minimum are not loaded into the I or Q DACs. 5 Measured while the digital inputs to the transmit interface are static and equal to 0 V or V DD. Specifications subject to change without notice.
-2-
REV. B
AD7011
ITx/QTx 20pF 20k
AD7011
20k 40k ITx / QTx 20pF
Figure 1. Analog Output Test Load Circuit
MASTER CLOCK TIMING otherwise noted.)
Parameter t1 t2 t3 300 100 100
(VAA = VDD = +5 V
10%; AGND = DGND = 0 V. All specifications are TMIN to TMAX unless
Limit at TA = -40 C to +85 C
Units ns min ns min ns min
Description MCLK Cycle Time MCLK High Time MCLK Low Time
1.6mA
IOL
t1 t2
MCLK
TO OUTPUT PIN +2.1V CL 100pF 200A IOH
t3
Figure 2. Master Clock (MCLK) Timing
Figure 3. Load Circuit for Digital Outputs
REV. B
-3-
AD7011 TRANSMIT SECTION TIMING
Parameter t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 10 t1 - 10 4097t1 + 70 10 t1 - 10 t1 + 70 3t1 + 70 64t1 32t1 32t1 50 0 3t1 124t1 7.5t9 30t1 10 10
(VAA = VDD = +5 V 10%; AGND = DGND = 0 V, fMCLK = 3.1104 MHz. All specifications are TMIN to TMAX unless otherwise noted.)
Units ns min ns max ns max ns min ns max ns max ns ns ns ns ns min ns min ns max ns max ns ns max ns max ns max Description Power Setup Time. MCLK rising edge, after Power high, to READY rising edge. BIN Setup Time. MCLK to READY propagation delay. MCLK rising edge, after BIN high, to first TxCLK rising edge. TxCLK Cycle Time. TxCLK High Time. TxCLK Low Time. TxCLK falling edge to TxDATA setup time. TxCLK falling edge to TxDATA hold time. BIN low setup to Last transmitted symbol after ramp down. BIN low hold to Last transmitted symbol after ramp down. Ramp Down cycle time after the last transmitted symbol. Last TxCLK falling edge to READY rising edge. Digital Output Rise Time. Digital Output Fall Time.
Limit at TA = -40 C to +85 C
MCLK
POWER
t4
READY
t7
t5
BIN
t6 t8 t9 t11 t12 t13 t10
X Y
TxCLK
TxDATA
k
k
Figure 4. Transmit Timing at the Start of a Tx Burst
MCLK
POWER
t17
READY BIN
t14 t15
TxCLK
t16
TxDATA XN+4 YN+4 XN+5 XN+8 YN+8
Figure 5. Transmit Timing at the End of a Tx Burst
-4-
REV. B
AD7011 ANALOG MODE TIMING
Parameter t20 t21 t22 t23 t24 15 15 15t1 16t1 15 15
(VAA = VDD = +5 V otherwise noted.)
10%. AGND = DGND = 0 V. All specifications are TMIN to TMAX unless
Units ns min ns min ns max ns ns min ns min Description MCLK Rising Edge to FRAME Setup Time. MCLK Rising Edge to FRAME Hold Time. FRAME Cycle Time. MCLK Rising Edge to Data Setup Time. MCLK Rising Edge to Data Hold Time.
Limit at TA = -40C to +85C
MCLK
t20
FRAME
t22
t21
t23 t24
I DATA DB9 DB8 DB1 DB0 DB9 DB8 DB7
Q DATA
DB9
DB8
DB1
DB0
DB9
DB8
DB7
Figure 6. Analog Mode Serial Interface Timing
Q MODULAR OUTPUT DURING FTEST
I
Table I.
MODE 1 0 1 0 1
MODE 2 0 0 1 1
Operation Digital TIA Mode Analog Mode FTEST Factory Test, Reserved
Figure 7. Modulator State During FTEST
Table II.
Mode of Operation Digital Mode Analog Mode
MODE 1 0 1
MODE 2 0 0
MCLK 3.1104 MHz 2.56 MHz
Digital Bit Rate 48.6 kHz N/A
DAC Update Rate N/A 160 kHz
REV. B
-5-
AD7011
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . . -0.3 V to VDD + 0.3 V Analog I/O Voltage to AGND . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . -65C to + 150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C SSOP JA Thermal Impedance . . . . . . . . . . . . . . . . +122C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD7011ARS
Temperature Range -40C to +85C
Package Description Shrink Small Outline Package
Package Option RS-24
SSOP PIN CONFIGURATION
POWER BIN (QDATA) TxCLK (FRAME) TxDATA (IDATA) V
DD
1 2 3 4 5 6 7 8 9 10 11 12 NC = NO CONNECT
24 23 22 21 20
BOUT AGND NC QTx QTx VAA AGND ITx ITx NC AGND BYPASS
DGND MCLK NC MODE1 NC MODE2 READY
AD7011
TOP VIEW (Not to Scale)
19 18 17 16 15 14 13
-6-
REV. B
AD7011
PIN FUNCTION DESCRIPTION SSOP Pin Number Mnemonic Function Positive power supply for analog section. Positive power supply for digital section. Analog ground for transmit section. Digital ground for transmit section.
POWER SUPPLY 19 VAA 5 VDD 14, 18, 23 AGND 6 DGND
ANALOG SIGNAL AND REFERENCE 13 BYPASS Reference decoupling output. A decoupling capacitor should be connected between this pin and AGND. Differential analog outputs for the I channel, representing true and complementary outputs of the I 16, 17 ITx, ITx waveform. Differential analog outputs for the Q channel, representing true and complementary outputs of the Q 21, 20 QTx, QTx waveform. TRANSMIT INTERFACE AND CONTROL 7 MCLK Master clock, digital input. When operating in Mode 0 (TIA Digital mode), this pin should be driven by a 3.1104 MHz CMOS compatible clock source in digital mode and by 2.56 MHz CMOS compatible clock source for analog mode. 3 TxCLK This is a dual function digital input/output. When operating in Mode 0 (TIA Digital mode), this pin is (FRAME) configured as a digital output, transmit clock. This may be used to clock in transmit data at 48.6 kHz. When operating in Mode 1 (analog mode), this pin is configured as a digital input, FRAME. This is used to frame the clocking in of 16-bit words when bypassing the /4 DQPSK modulator and directly loading the I and Q 10-bit DACs. 4 TxDATA This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this pin is used to (IDATA) clock in transmit data on the falling edge of TxCLK at a rate of 48.6 kHz. When operating in Mode 1 (Analog mode), I data is clocked in on the rising edge of MCLK. This data bypasses the /4 DQPSK modulator and is loaded into the 10-bit I DAC. 2 BIN (QDATA) This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this input is used to initiate the ramping up (BIN high) or down (BIN low) of the I and Q waveforms. When operating in Mode 1 (Analog mode), Q data is clocked in on the rising edge of MCLK. This data bypasses the /4 DQPSK modulator and is loaded into the 10-bit Q DAC. 24 BOUT Burst Out, digital output. This is the BIN input delayed by the pipeline delay, both digital and analog, of the AD7011. This can be used to turn on and off the RF amplifiers in synchronization with the I and Q waveforms. 1 POWER Transmit sleep mode, digital input. When this goes low, the AD7011 goes into sleep mode, drawing minimal current. When this pin goes high, the AD7011 is brought out of sleep mode and initiates a self-calibration routine to eliminate the offset between ITx & ITx and the offset between QTx & QTx. 12 READY Transmit ready, digital output. This output goes high once the self-calibration routine is complete. 9, 11 MODE1, Mode control, digital inputs. These are used to enter the AD7011 into three different operating modes, MODE2 see Table I. 8, 10, 15, 22 NC No Connects. These pins are no connects and should not be used as routes for other circuit signals.
REV. B
-7-
AD7011
TERMINOLOGY Error Vector Magnitude Signal to (Noise + Distortion) Ratio
This is a measure of the rms error vector introduced by the AD7011 where signal error vector is defined as the rms deviation of a transmitted symbol from its ideal position when filtered by an Ideal RRC Receive filter, as illustrated in Figure 8.
Gain Matching Between Channels
The is the gain matching between the I and Q outputs, measured when transmitting all zeros.
Offset Vector Magnitude
This is the measured ratio of signal to (noise + distortion) at the output of the transmit I and Q DACs. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise distortion) ratio for a sine wave is given by: SNR = (6.02N + 1.76) dB where N is the number of bits. Thus for an ideal 10-bit converter, SNR = 61.96 dB.
Q ERROR VECTOR
This is a measure of the offset vector introduced by the AD7011 as illustrated in Figure 8. The offset vector is calculated so as to minimize the rms error vector for each of the constellation points.
Output Signal Range and Different Output Range
The output signal range is the output voltage swing and dc bias level for each of the analog outputs. The different output range is the difference between ITx and ITx for the I channel and the difference between QTx and QTx for the Q Channel.
IS-54 Spurious Power
SIGNAL VECTOR
This is the rms sum of the spurious power measured at multiples of 30 kHz, in a root raised cosine window of 16.4 kHz, relative to twice the rms power in a RRC window in the 0 to 16.4 kHz band.
Signal Vector Magnitude
OFFSET VECTOR
0,0
I
This is the radius of the IQ constellation diagram as illustrated in Figure 8.
Figure 8.
-8-
REV. B
AD7011
CIRCUIT DESCRIPTION
TRANSMIT SECTION The transmit section of the AD7011 generates /4 DQPSK I and Q waveforms in accordance with TIA specification. This is accomplished by a digital /4 DQPSK modulator, which includes the root-raised cosine filters ( = 0.35), followed by two 10-bit DACs and on-chip reconstruction filters. The /4 DQPSK (Differential Quadrature Phase Shift Keying) digital modulator generates 10-bit I and Q data in response to the transmit data stream. The 10-bit I and Q DACs are filtered by on-chip reconstruction filters, which also generate differential analog outputs for both I and Q channels. The AD7011 transmit channel also provides an analog mode, where direct access to the I and Q DACs is provided, bypassing the /4 DQPSK modulator. This is provided so that the AD7011 transmit channel can also be used to perform the conversion and filtering of the analog waveforms required to emulate the existing analog cellular system. The /4 DQPSK modulator generates 10-bit I and Q data (Inphase and Quadrature) which are loaded into the I and Q 10-bit transmit DACs. Figure 9 shows the functional block diagram of the /4 DQPSK modulator. The transmit serial data (TxDATA) is first converted into Di-bit symbols [Xk, Yk], using a 2-bit serial to parallel converter. The data is then differentially encoded; symbols are transmitted as changes in phase rather than absolute phases. Each symbol represents a phase change, as illustrated in Table III, and this along with the previously transmitted symbol determines the next symbol to be transmitted. The differential phase encoder generates I and Q impulses [Ik, Qk] in response to the Di-bit symbols according to: Ik = COS [k-1 + k] Qk = SIN [k-1 + k]
/4 DQPSK DIGITAL MODULATOR I
Q
I
Figure 10. /4 DQPSK Constellation Diagram
Figure 10 illustrates the /4 DQPSK constellation diagram as described above, showing the eight possible states for [Ik, Qk]. The Ik and Qk impulses are then filtered by FIR raised root cosine filters ( = 0.35), generating 10-bit I and Q data. The FIR root raised cosine filters have an impulse response of 4 symbols.
Transmit Calibration
/4 DQPSK Modulator
When the transmit section is brought out of sleep mode (POWER high), the transmit section initiates a self-calibration routine to remove the offset between ITx and ITx and an offset between QTx and QTx. READY goes high on the completion of the self-calibration routine. Once READY goes high, BIN (Burst In) can be brought high to initiate a transmit burst.
Ramp-Up/Down Envelope Logic
X TxDATA 2-BIT SERIAL TO PARALLEL CONVERTER
k
k
Y
k
DIFFERENTIAL PHASE Q ENCODER k
ROOT-RAISED 10 COSINE FILTER ROOT-RAISED 10 COSINE FILTER
I DATA
The AD7011 provides on-chip envelope shaping logic, providing power shaping control for the beginning and end of a transmit burst. When BIN (Burst In) is brought high, the modulator is reset to a transmitting all zeros state (i.e., Xk = Yk = 0) and continues to transmit all zeros for the first three symbols, during which the ramp-up envelope goes from zero to full scale as illustrated in Figure 11. The next symbol to be transmitted is [I1, Q1], which represents the first two data bits clocked in after BIN going high, i.e., [X1, Y1].
Q DATA
Figure 9. /4 DQPSK Modulator Functional Block Diagram
Table III.
3 SYMBOLS 3 SYMBOLS 1 1 t -- + -- COS --- 2 2 3T
Xk 1 0 0 1
Yk 1 1 0 0
k
t 1 1 -- - -- COS --- 3T 2 2
-3 4 3 4 4 - 4
Figure 11. Ramp Envelope
When BIN is brought low, indicating the end of a transmit burst, the current Di-bit symbol [XN+4, YN+4] that the AD7011 is receiving will be the last symbol to be computed for the four symbol ramp-down sequence. Also the Nth symbol is the last active symbol prior to ramping down. However, because the impulse response is equal to 4 symbols, four additional symbols are required to fully compute the analog outputs when transmitting the (N+4)th symbol. Hence there will be eight subsequent TxCLKs, latching four additional Di-bit symbols: [XN + 5, YN + 5] to [XN + 8, YN + 8]. -9-
REV. B
AD7011
BIN TxCLK X1 Y1 XN YN XN+1 YN+1 XN+2 YN+2 XN+3 YN+3 XN+4 YN+4 XN+5 YN+5 XN+6 YN+6 XN+7 YN+7 XN+8 YN+8
TxDATA BOUT
= 480t1
(ITx-ITx), (QTx-QTx)
3 SYMBOL RAMP-UP ENVELOPE
3 SYMBOL RAMP-DOWN ENVELOPE
SYMBOL PHASE MAX EFFECT
0 0
0 0
0 0
I
1
I
N
I
N+1
I
N+2
I
N+3
I
N+4
Q1
QN
QN+1
QN+2
QN+3
QN+4
Figure 12. Transmit Burst
As Figure 12 illustrates, the ramp-down envelope reaches zero after three symbols, hence the fourth symbol does not actually get transmitted.
Reconstruction Filters
When POWER is brought low this puts the transmit section into a low power sleep mode, drawing minimal current. The analog outputs go high impedance while in low power sleep mode. MODE1 = VDD; MODE2 = DGND: Analog Mode Figure 6 shows the timing diagram for the transmit interface when operating in analog mode. In this mode the /4 DQPSK modulator is bypassed and direct access to the I and Q 10-bit DACs is provided. Loading of the I and Q DACs is accomplished using a 4 wire 16-bit serial interface. The pins TxCLK, TxDATA and BIN are all reconfigured as inputs, with the functions of FRAME, IDATA and QDATA respectively. I and Q data are loaded via the IDATA and QDATA pins and FRAME synchronizes the loading of the 16-bit I and Q words. FRAME should be brought high one clock cycle prior to the I and Q MSBs. Data is latched on the rising edge of MCLK, MSB first, where only the first 10 data bits are significant. Continuous updating of the I and Q DACs is required at a rate of MCLK/16. MODE1 = DGND; MODE2 = VDD: Frequency Test Mode A special FTEST (Frequency TEST) mode is provided for the customer, where no phase modulation takes place and the modulator outputs remain static. ITx is set to zero and QTx is set to full scale as Figure 7 illustrates. However, the normal ramp-up/ down envelope is still applied during the beginning and end of a burst. MODE1 = MODE2 = VDD: Factory Test Mode This mode is reserved for factory test only and should not be used by the customer for correct device operation.
The reconstruction filters smooth the DAC output signals, providing continuous time I and Q waveforms at the output pins. These are 4th order Bessel low-pass filters with a -3 dB frequency of approximately 25 kHz. The filters are designed to have a linear phase response in the passband and due to the reconstruction filters being on-chip, the phase mismatch between the I and Q transmit channels is kept to a minimum.
Transmit Section Digital Interface
MODE1 = MODE2 = DGND: Digital /4 DQPSK Mode Figures 4 and 5 shows the timing diagrams for the transmit interface when operating in TIA /4 DQPSK mode. POWER is sampled on the rising edge of MCLK. When POWER is brought high, the transmit section is brought out of sleep mode and initiates a self-calibration routine as described above. Once the self-calibration is complete, the READY signal goes high to indicate that a transmit burst can now begin. BIN (Burst in) is brought high to initiate a transmit burst and should only be brought high if the READY signal is already high. When BIN goes high, the READY signal goes low on the next rising edge of MCLK and TxCLK becomes active after a further three MCLK cycles. TxCLK can be used to clock out the transmit data from the ASIC or DSP on the rising edge of TxCLK and the AD7011 will latch TxDATA on the falling edge of TxCLK. When BIN is brought low, the AD7011 will continue to clock in the current Di-bit symbol (XN + 4, YN + 4) and will continue for a further 8 TxCLK cycles (four symbols). After the final TxCLK, READY goes high waiting for BIN to be brought high to begin the next transmit burst.
-10-
REV. B
AD7011
0 -10 -20
0 -10 -20
MAGNITUDE - dBs
0.1 1 10 FREQUENCY - kHz 100 1000
MAGNITUDE - dBs
-30 -40 -50 -60 -70 -80
-30 -40 -50 -60 -70 -80 0.1 1 10 FREQUENCY - kHz 100 1000
Figure 13. Reconstruction Filter Frequency Response for the I and Q DACs, MCLK = 2.56 MHz
1.2
Figure 16. Reconstruction Filter Frequency Response for the I and Q DACs, MCLK = 3.1104 MHz
1.2
0.8
Q Channel - Volts Q Channel - Volts
0.8
0.4
0.4
0
0
-0.4
-0.4
-0.8
-0.8
-1.2 -1.2
-0.8
-0.4
0
0.4
0.8
1.2
-1.2 -1.2
-0.8
-0.4
0
0.4
0.8
1.2
I Channel - Volts
I Channel - Volts
Figure 14. AD7011 I vs. Q Waveforms When Transmitting Random Data
1.2
Figure 17. AD7011 I vs. Q Waveforms Filtered by an Ideal Root Raised Cosine Receive Filter
1.2
0.8
Q Channel - Volts Q Channel - Volts
0.8
0.4
0.4
0
0
-0.4
-0.4
-0.8
-0.8
-1.2 -1.2
-0.8
-0.4
0
0.4
0.8
1.2
-1.2 -1.2
-0.8
-0.4
0
0.4
0.8
1.2
I Channel - Volts
I Channel - Volts
Figure 15. AD7011 Transmit Constellation Diagram
Figure 18. AD7011 Constellation Diagram When Filtered by an Ideal Root Raised Cosine Receive Filter
REV. B
-11-
AD7011
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead SSOP (RS-24)
C1780a-5-7/94
24
13
0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) 1 12
PIN 1
0.328 (8.33) 0.318 (8.08)
0.07 (1.78) 0.066 (1.67)
0.008 (0.203) 0.002 (0.050)
0.037 (0.94) 8 0.022 (0.559) 0 0.009 (0.229) 0.005 (0.127) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.0256 (0.65) BSC
-12-
REV. B
PRINTED IN U.S.A.

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